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XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a digital logic gate that gives a true (1 or HIGH) output when the number of true inputs is odd. An XOR gate implements an exclusive or ( ↮ {\displaystyle \nleftrightarrow } ) from mathematical logic; that is, a true output results if one, and only one, of the inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a false output results. XOR represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the output is false. A way to remember XOR is "must have one or the other but not both". An XOR gate may serve as a "programmable inverter" in which one input determines whether to invert the other input, or to simply pass it along with no change. Hence it functions as a inverter (a NOT gate) which may be activated or deactivated by a switch. XOR can also be viewed as addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. A half adder consists of an XOR gate and an AND gate. The gate is also used in subtractors and comparators. The algebraic expressions A ⋅ B ¯ + A ¯ ⋅ B {\displaystyle A\cdot {\overline {B}}+{\overline {A}}\cdot B} or ( A + B ) ⋅ ( A ¯ + B ¯ ) {\displaystyle (A+B)\cdot ({\overline {A}}+{\overline {B}})} or ( A + B ) ⋅ ( A ⋅ B ) ¯ {\displaystyle (A+B)\cdot {\overline {(A\cdot B)}}} or A ⊕ B {\displaystyle A\oplus B} all represent the XOR gate with inputs A and B. The behavior of XOR is summarized in the truth table shown on the right. Symbols There are three schematic symbols for XOR gates: the traditional ANSI and DIN symbols and the IEC symbol. In some cases, the DIN symbol is used with ⊕ instead of ≢. For more information see Logic Gate Symbols. The "=1" on the IEC symbol indicates that the output is activated by only one active input. The logic symbols ⊕, Jpq, and ⊻ can be used to denote an XOR operation in algebraic expressions. C-like languages use the caret symbol ^ to denote bitwise XOR. (Note that the caret does not denote logical conjunction (AND) in these languages, despite the similarity of symbol.) Implementation The XOR gate is most commonly implemented using MOSFETs circuits. Some of those implementations include: AND-OR-Invert XOR gates can be implemented using AOI logic. CMOS The metal–oxide–semiconductor (CMOS) implementations of the XOR gate corresponding to the AOI logic above are shown below. On the left, the nMOS and pMOS transistors are arranged so that the input pairs A ⋅ B ¯ {\displaystyle A\cdot {\overline {B}}} and A ¯ ⋅ B {\displaystyle {\overline {A}}\cdot B} activate the 2 pMOS transistors of the top left or the 2 pMOS transistors of the top right respectively, connecting Vdd to the output for a logic high. The remaining input pairs A ⋅ B {\displaystyle A\cdot B} and A ¯ ⋅ B ¯ {\displaystyle {\overline {A}}\cdot {\overline {B}}} activate each one of the two nMOS paths in the bottom to Vss for a logic low. If inverted inputs (for example from a flip-flop) are available, this gate can be used directly. Otherwise, two additional inverters with two transistors each are needed to generate A ¯ {\displaystyle {\overline {A}}} and B ¯ {\displaystyle {\overline {B}}} , bringing the total number of transistors to twelve. The AOI implementation without inverted input has been used, for example, in the Intel 386 CPU. Transmission gates The XOR gate can also be implemented by the use of Transmission gates with pass transistor logic. This implementation uses two Transmission gates and two inverters not shown in the diagram to generate A ¯ {\displaystyle {\overline {A}}} and B ¯ {\displaystyle {\overline {B}}} for a total of eight transistors, four less than in the previous design. The XOR function is implemented by passing through to the output the inverted value of A when B is high and passing the value of A when B is at a logic low. so when both inputs are low the transmission gate at the bottom is off and the one at the top is on and lets A through which is low so the output is low. When both are high only the one at the bottom is active and lets the inverted value of A through and since A is high the output will again be low. Similarly if B stays high but A is low the output would be A ¯ {\displaystyle {\overline {A}}} which is high as expected and if B is low but A is high the value of A passes through and the output is high completing the truth table for the XOR gate. The trade-off with the previous implementation is that since transmission gates are not ideal switches, there is resistance associated with them, so depending on the signal strength of the input, cascading them may degrade the output levels. Optimized pass-gate-logic wiring The previous transmission gate implementation can be further optimized from eight to six transistors by implementing the functionality of the inverter that generates A ¯ {\displaystyle {\overline {A}}} and the bottom pass-gate with just two transistors arranged like an inverter but with the source of the pMOS connected to B .... Discover the Dickon Ross Doug Lowe popular books. Find the top 100 most popular Dickon Ross Doug Lowe books.